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HA-5033
Data Sheet February 6, 2006 FN2924.8
250MHz Video Buffer
The HA-5033 is a unity gain monolithic IC designed for any application requiring a fast, wideband buffer. Featuring a bandwidth of 250MHz and outstanding differential phase/ gain characteristics, this high performance voltage follower is an excellent choice for video circuit design. Other features, which include a minimum slew rate of 1000V/s and high output drive capability, make the HA-5033 applicable for line driver and high speed data conversion circuits. The high performance of this product is a result of the Intersil Dielectric Isolation process. A major feature of this process is that it produces both PNP and NPN high frequency transistors which makes wide bandwidth designs, such as the HA-5033, practical. Alternative process methods typically produce a lower AC performance.
Features
* Differential Phase Error . . . . . . . . . . . . . . . . 0.02 Degrees * Differential Gain Error . . . . . . . . . . . . . . . . . . . . . . 0.03% * High Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . 1100V/s * Wide Bandwidth (Small Signal) . . . . . . . . . . . . . . 250MHz * Wide Power Bandwidth . . . . . . . . . . . . . . DC to 17.5MHz * Fast Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ns * High Output Drive. . . . . . . . . . . . . . 10V With 100 Load * Wide Power Supply Range . . . . . . . . . . . . . 5V to 16V * Replace Costly Hybrids
Applications
* Video Buffer * High Frequency Buffer
Ordering Information
PART NUMBER PART MARKING TEMP. RANGE (C) -55 to 125 0 to 75 PACKAGE PKG. DWG. #
* Isolation Buffer * High Speed Line Driver * Impedance Matching * Current Boosters
HA2-5033-2 HA2-5033-2 HA3-5033-5 HA3-5033-5
12 Pin Metal Can T12.C 8 Ld PDIP E8.3
Pinouts
HA-5033 (PDIP) TOP VIEW
V+ 1 NC NC IN 2 3 4 8 7 6 5 OUT NC SUBSTRATE V-
* High Speed A/D Input Buffers * Related Literature - AN548, Designer's Guide for HA-5033
HA-5033 (METAL CAN) TOP VIEW
V+ NC CASE 2 NC NC 3 4 5 6 +IN NC NC 7 8 NC 1 12 11 10 9 VNC OUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HA-5033
Absolute Maximum Ratings
Voltage Between V+ and V- Pins. . . . . . . . . . . . . . . . . . . . . . . . 40V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VOutput Current (Peak) (50ms On/1 Second Off) . . . . . . . . . 200mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . 2000V
Thermal Information
Thermal Resistance (Typical, Note 2) JA (C/W) JC (C/W) Metal Can Package . . . . . . . . . . . . . . . 65 34 PDIP Package . . . . . . . . . . . . . . . . . . . 120 N/A Maximum Junction Temperature (Note 1) . . . . . . . . . . . . . . . . . 175C Maximum Junction Temperature (Plastic Packages) . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C
Operating Conditions
Temperature Ranges (Note 3) HA-5033-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C HA-5033-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 75C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below 175C for the metal can package, and below 150C for the plastic packages (See Figure 5.). 2. JA is measured with the component mounted on an evaluation PC board in free air. 3. The maximum operating temperature may have to be derated depending on the output load condition. See Figure 5 for more information.
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS Offset Voltage
VSUPPLY = 12V, RS = 50, RL = 100, CL = 10pF, Unless Otherwise Specified TEST CONDITIONS TEMP. (C) HA-5033-2 MIN TYP MAX MIN HA-5033-5 TYP MAX UNITS
25 Full
-
5 6 33 20 30 3 1.6 20
15 25 35 50 -
-
5 6 33 20 30 3 1.6 20
15 25 35 50 -
mV mV V/C A A M pF VP-P
Average Offset Voltage Drift Bias Current
Full 25 Full
Input Resistance Input Capacitance Input Noise Voltage TRANSFER CHARACTERISTICS Voltage Gain RL = 100 RL = 1k RL = 100 -3dB Bandwidth OUTPUT CHARACTERISTICS Output Voltage Swing RL = 100 RL = 1k, VS = 15V Output Current Output Resistance Full Power Bandwidth Full Power Bandwidth (Note 4) TRANSIENT RESPONSE Rise Time Propagation Delay VOUT = 500mV VOUT = 1VRMS , RL = 1k 10Hz to 100MHz
25 25 25
25 25 Full 25
0.93 0.93 0.92 -
0.99 250
-
0.93 0.93 0.92 -
0.99 250
-
V/V V/V V/V MHz
Full Full 25 25 25 25
8 11 80 15.9
10 12 100 8 146 17.5
-
8 11 80 15.9
10 12 100 8 146 17.5
-
V V mA MHz MHz
25 25
-
4.6 1
-
-
4.6 1
-
ns ns
2
FN2924.8
HA-5033
Electrical Specifications
PARAMETER Overshoot Slew Rate (Note 4) Settling Time to 0.1% Differential Phase Error (Note 5) Differential Gain Error (Note 5) POWER SUPPLY CHARACTERISTICS Supply Current 25 Full Power Supply Rejection Ratio Harmonic Distortion NOTES: 4. VSUPPLY = 15V, VOUT = 10V, RL = 1k. 5. Differential gain and phase error are nonlinear signal distortions found in video systems and are defined as follows: Differential gain error is defined as the change in amplitude at the color subcarrier frequency as the picture signal is varied from blanking to white level. Differential phase error is defined as the change in the phase of the color subcarrier as the picture signal is varied from blanking to white level. RL = 300. VIN = 1VRMS at 100kHz Full 25 54 21 21 <0.1 25 30 54 21 21 <0.1 25 30 mA mA dB % VSUPPLY = 12V, RS = 50, RL = 100, CL = 10pF, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP. (C) 25 25 25 25 25 HA-5033-2 MIN 1 TYP 3 1.1 50 0.02 0.03 MAX MIN 1 HA-5033-5 TYP 3 1.1 50 0.02 0.03 MAX UNITS % V/ns ns Degree %
Test Circuits and Waveforms
+15V 0.1F +12V 0.1F
IN RL 0.1F -15V
OUT
IN 100 0.1F -12V
OUT
FIGURE 1. SLEW RATE AND SETTLING TIME
FIGURE 2. TRANSIENT RESPONSE
10V INPUT 0V 90% 10% t
500mV INPUT 0V OVERSHOOT V SLEW RATE = V/t SETTLING TIME ERROR BAND 10mV FROM FINAL VALUE
OUTPUT
90% OUTPUT 10%
NOTE: Measured on both positive and negative transitions.
FIGURE 3. SETTLING TIME AND SLEW RATE
FIGURE 4. RISE TIME AND OVERSHOOT
3
FN2924.8
HA-5033 Test Circuits and Waveforms
(Continued)
VIN VIN 0V
0V
VOUT 0V
VOUT 0V
TA = 25C, RS = 50, RL = 100 +10V RESPONSE
TA = 25C, RS = 50, RL = 1k +10V RESPONSE
500mV VIN
0V 500mV VOUT 0V
TA = 25C, RS = 50, RL = 100 PULSE RESPONSE
Schematic Diagram
V+ R5 Q15 R4 R2 R12
Q11 Q6 Q10
Q16
Q12 R9 Q19 R6 VIN Q3 R8 Q4 Q8 Q7
Q1 R11 VOUT R10 Q2 Q5 Q9 R13
Q17
Q13
Q18 R3 V-
Q14 R1
4
FN2924.8
HA-5033 Application Information
Layout Considerations
The wide bandwidth of the HA-5033 necessitates that high frequency circuit layout procedures be followed. Failure to follow these guidelines can result in marginal performance. Probably the most crucial of the RF/video layout rules is the use of a ground plane. A ground plane provides isolation and minimizes distributed circuit capacitance and inductance which will degrade high frequency performance. IC sockets contribute inter-lead capacitance which limits device bandwidth and should be avoided. Pin 6 can be tied to either supply, grounded, or simply not used. But to optimize device performance and improve isolation, it is recommended that this pin be grounded. Other considerations are proper power supply bypassing and keeping the input and output connections as short as possible which minimizes distributed capacitance and reduces board space. It is also recommended that the bypass capacitors be connected close to the HA-5033 (preferably directly to the supply pins).
Figure 5 is based on: T JMAX - T A P DMAX = ----------------------------- JA Where: TJMAX = Maximum Junction Temperature of the Device TA = Ambient Temperature JA = Junction to Ambient Thermal Resistance
MAXIMUM TOTAL POWER DISSIPATION (W) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 25 45 65 85 105 125 TEMPERATURE (C) QUIESCENT PD = 0.72W AT VS = 12V, ICC = 30mA PDIP CAN
Power Supply Decoupling
For optimum device performance, it is recommended that the positive and negative power supplies be bypassed with capacitors to ground. Ceramic capacitors ranging in value from 0.01F to 0.1F will minimize high frequency variations in supply voltage. Solid tantalum capacitors 1F or larger will optimize low frequency performance.
FIGURE 5. MAXIMUM POWER DISSIPATION vs TEMPERATURE
Typical Applications
+12V 0.1F
(Also see Application Note AN548)
V+ HA-2539 VIDEO SIGNAL INPUT RM 50 RG -58 V+ VIDEO OUTPUT
R1
+ 60
HA-5033
V900 V-
RS VIN
75 75
5
12 10
11
R2
15 50 RL
0.1F -12V
100
FIGURE 6. VIDEO COAXIAL LINE DRIVER 50 SYSTEM
FIGURE 7. VIDEO GAIN BLOCK
5
FN2924.8
HA-5033 Typical Applications
(Also see Application Note AN548) (Continued)
0V VIN
VIN 0V
0V VOUT
VOUT 0V
TA = 25C, RS = 50, RM = RL = 50 RL 1 V O = V IN ---------------------- = -- V IN RL + RM 2 POSITIVE PULSE RESPONSE
TA = 25C, RS = 50, RM = RL = 50 RL 1 V O = V IN ---------------------- = -- V IN RL + RM 2 NEGATIVE PULSE RESPONSE
Typical Performance Curves
40 8 OFFSET VOLTAGE (mV) 7 6 5 4 3 2 1 -80 VS = 5V 0 -55 -25 25 75 TEMPERATURE (C) 125 VS = 10V VS = 12V VS = 15V VS = 10V 30 VS = 5V
INPUT BIAS CURRENT (A)
20 VS = 12V 10 VS = 15V
-40
0
80 40 TEMPERATURE (C)
120
160
FIGURE 8. INPUT OFFSET VOLTAGE vs TEMPERATURE
30 VS = 15V SUPPLY CURRENT (mA) SLEW RATE (V/s)
FIGURE 9. INPUT BIAS CURRENT vs TEMPERATURE
3000 VS = 15V, VIN = 10V
FALL (RL = 1k) 2000 FALL (RL = 100)
20 VS = 12V VS = 10V VS = 5V 10
1000 RISE (RL = 1k) RISE (RL = 100)
0 -55
-25
25 TEMPERATURE (C)
75
125
-55
-25
25 TEMPERATURE (C)
75
125
FIGURE 10. SUPPLY CURRENT vs TEMPERATURE
FIGURE 11. SLEW RATE vs TEMPERATURE
6
FN2924.8
HA-5033 Typical Performance Curves
2400 2200 VS = 15V, RL = 1k TA = 25C, VIN = 10V 2000 1800 SLEW RATE (V/s) 1600 1400 1200 1000 800 600 400 200 0 100 1000 5000 10,000 RISE FALL SLEW RATE (V/s)
(Continued)
1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0
VS = 15V, RL = 100 TA = 25C, VIN = 10V
FALL
RISE
100
1000
5000
10,000
CAPACITANCE (pF)
CAPACITANCE (pF)
FIGURE 12. SLEW RATE vs LOAD CAPACITANCE
FIGURE 13. SLEW RATE vs LOAD CAPACITANCE
80 60 OUTPUT INPUT VOS (mV) 40 20 0 -20 -40 -60
VS = 15V, TA = 25C
900 RL = 1k 700 OUTPUT INPUT VOS (mV) 500 300
VS = 15V, TA = 25C
RL = 50
RL = 10k RL = 10k
RL = 100 100 0 -100 RL = 100 -300 -500 -700 -900 -10 RL = 50 -8 -6 -4 -2 0 +2 +4 +6 +8 +10
RL = 1k -8 -6 -4 -2 0 +2 +4 +6 +8 +10
-80 -10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 14. GAIN ERROR vs INPUT VOLTAGE
FIGURE 15. GAIN ERROR vs INPUT VOLTAGE
160 VS = 15V, VO = 10V 140 OUTPUT INPUT VOS (mV) 120 100 RL = 1k 80 60 40 20 VIN - VOUT (mV) VS = 15, TA = 25C 800 700 600 500 400 300 200 100 0 -55 -25 25 TEMPERATURE (C) 75 125 10 20 30 40 50 60 70 IOUT (mA) 80 90 100 110 120 VOUT = 0 SOURCING CURRENT VOUT = 0 SINKING CURRENT VOUT = -10 VOUT = +10
FIGURE 16. GAIN ERROR vs TEMPERATURE
FIGURE 17. VIN - VOUT vs IOUT
7
FN2924.8
HA-5033 Typical Performance Curves
180 Y21 135 PHASE ANGLE (DEGREES) 10-1 90 45 0 Y22 -45 -90 -135 -180 106 Y12 Y11 MAGNITUDE (S) 10-2 Y11 Y12 Y22 Y21
(Continued)
1 Y21, Y22
10-3
10-4
Y11 Y12
107
108
109
10-5 106
FREQUENCY (Hz)
107 108 FREQUENCY (Hz)
109
FIGURE 18. Y - PARAMETERS PHASE vs FREQUENCY
FIGURE 19. Y - PARAMETER MAGNITUDE vs FREQUENCY
POWER SUPPLY REJECTION RATIO (dB)
70 60 50 40 30 20 10
TOTAL HARMONIC DISTORTION (%)
VS = 12V, TA = 25C
0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01
VS = 12V, RL = 100 VIN = 1VRMS
1K
10K
100K FREQUENCY (Hz)
1M
10M
100
1K 10K FREQUENCY (Hz)
100K
FIGURE 20. POWER SUPPLY REJECTION RATIO vs FREQUENCY
FIGURE 21. TOTAL HARMONIC DISTORTION vs FREQUENCY
1.0 TOTAL HARMONIC DISTORTION (%)
PEAK TO PEAK OUTPUT VOLTAGE (V)
VS = 12V RL = V = 12V, RL = 100 100 f = 100kHz
TA = 25C 28 24 20 16
VS = 15V VS = 12V
0.1
VS = 10V 12 8 4 VS = 5V 0 100 200 300 400 500 600 700 800 900 1K LOAD RESISTANCE ()
0.01
0
1
2 INPUT VOLTAGE (RMS)
3
FIGURE 22. TOTAL HARMONIC DISTORTION vs INPUT VOLTAGE
FIGURE 23. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
8
FN2924.8
HA-5033 Typical Performance Curves
6.0 5.5 OUTPUT VOLTAGE (VRMS) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 10K 100K 1M 10M FREQUENCY (Hz) 100M 1G NO HEAT SINK IN FREE AIR
(Continued)
VS = 15V, RL = 100 OUTPUT VOLTAGE (VRMS)
6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 10K 100K NO HEAT SINK IN FREE AIR
VS = 15V, RL = 1k
1M 10M FREQUENCY (Hz)
100M
1G
FIGURE 24. OUTPUT SWING vs FREQUENCY (NOTE) NOTE:
FIGURE 25. OUTPUT SWING vs FREQUENCY (NOTE)
This curve was obtained by noting the output voltage necessary to produce an observable distortion for a given frequency. If higher distortion is acceptable, then a higher output voltage for a given frequency can be obtained. However, operating the HA-5033 with increased distortion (to the right of curve shown), will also be accompanied by an increase in supply current. The resulting increase in chip temperature must be considered and heat sinking will be necessary to prevent thermal runaway. This characteristic is the result of the output transistor operation. If the signal amplitude or signal frequency or both are increased beyond the curve shown, the NPN, PNP output transistors will approach a condition of being simultaneously on. Under this condition, thermal runaway can occur.
9
FN2924.8
HA-5033 Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): Unbiased TRANSISTOR COUNT: 20 PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5033
IN
V+
OUT
V-
10
FN2924.8
HA-5033 Metal Can Packages (Can)
A L REFERENCE PLANE
T12.C
12 LEAD METAL CAN PACKAGE e1 SYMBOL INCHES MIN 0.130 0.016 0.016 0.585 0.540 MAX 0.150 0.019 0.021 0.615 0.560 MILLIMETERS MIN 3.30 0.41 0.41 14.86 13.72 MAX 3.81 0.48 0.53 15.62 14.22 NOTES 2 3 Rev. 0 5/18/94
A A OD OD1
A e
N 2 1 k1
Ob Ob2 OD OD1
k F BASE METAL LEAD FINISH
e e1 F k
0.400 BSC 0.100 BSC 0.020 0.027 0.027 0.500 12 0.040 0.034 0.045 0.560
10.16 BSC 2.54 BSC 0.51 0.69 0.69 12.70 12 1.02 0.86 1.14 14.22
Ob
Ob2
k1 L
SECTION A-A
N
NOTES: 1. The reference, base, and seating planes are the same for this variation. 2. Measured from maximum diameter of the product. 3. N is the maximum number of terminal positions. 4. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 5. Controlling dimension: INCH.
11
FN2924.8
HA-5033 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 8
2.93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN2924.8

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